Serial interfaces play an important role in high-speed chip-to-chip signaling. By transferring serialized data along a serial data path, or link, chip pin counts may be minimized while increasing data rates between the chips. While numerous serial protocols exist to enable transmission and receipt of high-speed packet data, very few adequately address latency issues that may arise during data transmission and reception.
For example, many protocols employ training words to periodically update link parameters to maintain optimal link operation. The training words may be transmitted and received at initialization, or periodically sent and received at regular intervals. In this manner, certain alignment, scrambling, and error detection functions may be carried out to minimize link downtime.
One specific protocol, known as the Interlaken serial protocol, organizes training words into per-lane “meta-frames” that also include a portion of a data packet payload, the data payload being spread across multiple meta-frames, and in-between meta-frames. Each link partner that communicates via the protocol establishes a programmed meta-frame word length that repeats during normal link operations, effectively inserting the training control words into meta-frame words for each link every meta-frame interval.
FIG. 1 illustrates a generalized organization of data and training words along multiple serial lanes LANE0-LANE3 in accordance with the Interlaken protocol. A first data payload field 102 for the packet is shown with a plurality of data words DATA that are striped along the serial lane interface beginning with Lane 0 (as shown by the arrows interconnecting each column of data words). Each lane is organized into multiple link frames 104 that each include several of the data words along with multiple training words TRAIN. The meta-frames have programmable word lengths that repeat every associated programmed interval. In the example of FIG. 1, the programmed meta-frame length is shown as eight words.
One problem with the Interlaken protocol involves non-deterministic latency associated with transmitting request link frames from one chip at a first frame length and receiving related response frames from the other chip at a different programmed link frame length. FIG. 2 illustrates the problem, which results, for one reason, because of the independence between the respective meta-frame programming on each chip. Example A shows a round-trip latency of “Latency A” that includes the latency associated with a request link frame RQ_FM_A framed according to the Interlaken meta-frame methodology, and additional latency associated with a response link frame RESP_FM_A also framed in accordance with the Interlaken protocol. Example B shows the same arrangement, but with the response words beginning with RESP_FM_D responding sooner than frame RESP_FM_A, thus exhibiting a shorter latency “Latency B” than the latency from Example A. Thus, although the latency in the second example is less than the first, queuing logic on the requesting chip often needs to account for at least the worst-case latency in order to efficiently pipeline response packets to the request chip core circuitry. This is undesirable from an efficiency and bandwidth standpoint.
Thus, the need exists for a serial data method and apparatus that minimizes non-deterministic latency for a serial link while still providing periodic training capabilities in the system.
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